Former Intel CEO Patrick Gelsinger Backs Z2RAM as a Potential Breakthrough for AI Memory
Former Intel CEO Patrick Gelsinger has voiced strong support for Nagare Labs and its emerging Z2RAM memory technology, describing it as a promising new approach that could bring together the strongest qualities of SRAM, DRAM, and flash memory.
The technology is being positioned as a possible alternative or complement to high-bandwidth memory, especially as AI chips demand faster, denser, and more power-efficient memory solutions. One of Z2RAM’s biggest advantages is that it can be integrated directly onto the logic chip, reducing the physical distance data must travel and potentially improving both speed and energy efficiency.
Modern processors rely on several different types of memory, each serving a specific purpose. DRAM is widely used as main system memory and is also a key foundation for today’s high-bandwidth memory used in AI accelerators and advanced GPUs. It holds data before that information is sent to the processor.
SRAM, on the other hand, is typically placed much closer to the CPU or GPU. It acts as cache memory, allowing processors to access critical data quickly with very low latency. Then there is NAND flash, which is used for long-term storage before data is moved into DRAM for active use.
Each memory type has strengths and weaknesses. DRAM offers density, SRAM delivers speed, and flash memory has continued to scale effectively through vertical stacking. Nagare Labs’ Z2RAM aims to combine these benefits into one new memory design.
A key problem in the semiconductor industry is that SRAM scaling has become increasingly difficult. Traditional SRAM cells use six transistors, and shrinking them further introduces major engineering challenges, including leakage current and material-related limitations. As AI chips grow larger and more complex, SRAM can take up a significant amount of valuable chip area.
NAND flash has followed a different path. Instead of relying only on shrinking features horizontally, manufacturers have stacked layers vertically, with modern designs exceeding 300 layers in some cases. This allows more storage capacity without dramatically increasing the chip’s surface area.
Z2RAM takes inspiration from this vertical scaling approach while attempting to preserve the low-latency benefits of SRAM. By stacking memory vertically and integrating it directly with logic, the technology could reduce chip area pressure while maintaining fast access times.
Unlike traditional 1T1C memory designs, which use one transistor and one capacitor, Z2RAM removes the capacitor. Instead, it relies on a two-transistor structure. According to Nagare Labs co-founder Suman Datta, who is also associated with the Georgia Institute of Technology, the design uses the gate capacitance of the second transistor to store charge.
This change could make the memory more scalable while avoiding some of the limitations found in conventional SRAM and DRAM designs.
Gelsinger has expressed optimism about the potential of Z2RAM, saying the technology appears to combine the density of DRAM, the speed of SRAM, and the scalability of flash memory. His investment firm, Playground Global, is also backing Nagare Labs, further highlighting confidence in the company’s direction.
He also compared Z2RAM’s potential value to high-bandwidth memory, which is currently one of the most important memory technologies for AI computing. HBM offers strong performance and density, but it also comes with limitations involving power consumption, physical layout constraints, and bandwidth delivery at the package edge.
According to Gelsinger, Z2RAM could offer improvements in density, speed, and power efficiency, making it especially relevant as the AI hardware market continues to expand.
The timing is important. AI accelerators, GPUs, and next-generation processors are increasingly limited not just by raw compute power, but by how quickly and efficiently they can access memory. As models grow larger and workloads become more demanding, memory bandwidth, latency, and energy use are becoming critical factors in chip design.
If Z2RAM can deliver on its promises, it could become an important technology for future AI chips, data center processors, and advanced computing systems. By placing dense, fast memory closer to logic, Nagare Labs may be addressing one of the biggest bottlenecks in modern semiconductor design.
While the technology still has to prove itself at scale, Gelsinger’s support gives Z2RAM added credibility. The memory market is highly competitive, but the demand for better AI memory solutions is only increasing. A technology that can combine high density, fast access, lower power use, and improved scalability could attract serious attention across the semiconductor industry.
For now, Z2RAM remains an emerging technology to watch. But with rising pressure on conventional SRAM scaling and growing demand for AI-focused memory innovation, Nagare Labs may be working on a solution that arrives at exactly the right time.
