Tesla has reduced the memory specifications for its upcoming AI5 and AI6 chips as the global memory supply crunch continues to pressure hardware makers. Elon Musk says the change was necessary to secure enough chip volume for Optimus production while also lowering costs.
According to Musk, the Tesla AI5 chip will now include 72 GB of LPDDR5 memory, down from the previously expected 144 GB. The AI6 chip is also being scaled back, with 144 GB of LPDDR6 memory planned after a reduction of roughly one-third.
The move highlights how tight the memory market has become, especially as demand rises from artificial intelligence, robotics, data centers, and advanced automotive systems. Tesla is preparing its next-generation AI chips not only for its Full Self-Driving compute platform but also for Optimus, the company’s humanoid robot.
Despite the memory downgrade, Musk said Tesla does not expect a meaningful impact on Optimus performance. He explained that reducing DRAM was the only practical way to obtain enough production volume for the robot program while significantly cutting costs.
The Tesla AI5 chip is expected to be a major step forward for the company’s in-house AI hardware strategy. It reportedly uses a half-reticle physical design, with a large central compute die surrounded by 12 DRAM modules. The chip is planned for fabrication by TSMC and Samsung using advanced 2nm-class manufacturing technology.
Performance expectations remain ambitious. AI5 is said to deliver around 2,000 to 2,500 TOPS, placing it in the same broad performance conversation as high-end AI accelerators. A single-chip AI5 configuration has been compared to NVIDIA’s H100 class of hardware, while a dual-chip version is expected to compete more directly with newer Blackwell-class systems.
Trial production of AI5 is already underway at Samsung’s Taylor facility in Texas, with volume production expected in 2027. The chip is central to Tesla’s long-term goal of controlling more of its AI stack, from vehicle autonomy to robotics.
Tesla’s AI6 and AI6.5 chips are also expected to use manufacturing from both TSMC and Samsung. While the DRAM allocation has been cut, these chips are still expected to rely heavily on SRAM to boost effective memory bandwidth. Musk previously stated that roughly half of the chips’ AI computation accelerators are dedicated to SRAM, which can offer much higher bandwidth than DRAM for calculations that fit inside the cache.
That design choice may help explain why Tesla believes the memory reduction will have little effect on Optimus. If key workloads can stay inside fast SRAM cache, the robot may not depend as heavily on larger amounts of external DRAM.
Still, the decision comes at a time when memory demand from physical AI is expected to grow rapidly. Industry expectations suggest that each humanoid robot could eventually require around 200 GB of DRAM and multiple terabytes of NAND storage. If humanoid robots move from prototypes to mass-market products, they could become a major new driver of global memory and storage consumption by the end of the decade.
For Tesla, the AI5 and AI6 memory downgrade appears to be a strategic trade-off. The company is prioritizing manufacturability, cost control, and production scale over maximum memory capacity. If Musk is correct that Optimus performance remains largely unaffected, the move could help Tesla accelerate its robotics ambitions at a lower cost.
The bigger takeaway is that AI hardware design is increasingly being shaped not just by performance targets, but by supply chain realities. As memory remains one of the most contested components in the AI boom, even companies building some of the world’s most advanced chips may need to adjust specifications to secure enough production capacity.
