Cadence and TSMC Expand Partnership for A14, AI Chips, HPC, and Advanced 3D-IC Design
Cadence and TSMC are deepening their collaboration to help chip designers move faster on the next generation of AI and high-performance computing silicon. The expanded partnership brings certified Cadence design flows to TSMC’s advanced A14 process technology, adds support for A16 and N2P, and strengthens the ecosystem around chiplet-based systems, advanced packaging, and silicon-proven IP.
The move is especially important as AI accelerators, hyperscale processors, networking chips, and high-bandwidth memory systems become more complex. Modern semiconductor designs increasingly rely on multiple chiplets, tighter power and timing targets, faster interconnects, and advanced packaging technologies. By certifying key tools and IP across TSMC’s leading process nodes, Cadence is aiming to reduce design risk and help customers reach tape-out more quickly.
Cadence has now achieved certification for digital full-flow, signoff, and custom/analog design flows on TSMC A14 and A16 technologies. These flows include major Cadence platforms such as the Innovus Implementation System, Cerebrus Intelligent Chip Explorer, Genus Synthesis Solution, Tempus Timing and ECO Solution, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Pegasus Verification System, Liberate Characterization Portfolio, and EMX Planar 3D Solver.
For chipmakers, this certification means they can begin advanced design work on TSMC’s latest process technologies with greater confidence. Certified flows are essential because they help ensure that design tools are aligned with the process rules, performance requirements, and manufacturing expectations of a new node.
Cadence is also strengthening its custom and analog design capabilities for TSMC A16 and A14. Virtuoso Studio solutions now support design-rule-correct layout generation and automated design migration for these advanced nodes. According to Cadence, these improvements can reduce layout iterations by up to 2.5 times while improving first-pass success for AI, HPC, and mobile system-on-chip designs.
The A14 process is positioned as a major platform for next-generation computing, and Cadence is preparing a broad IP portfolio to support it. UCIe-64G IP has already taped out on TSMC A14, while LPDDR6 IP is currently in development. Cadence is also prioritizing high-performance memory and connectivity IP needed for compute chiplets, AI accelerators, and advanced networking platforms.
Artisan Foundation IP and mixed-signal IP for TSMC A14 are also in development, with availability expected in the fourth quarter of 2026. This portfolio is expected to include standard cells, GPIO, and Memory Compilers optimized for HPC, AI, and networking applications.
TSMC N2P is also gaining deeper Cadence support. Cadence analog, digital, and signoff flows have been certified for the N2P process, giving infrastructure AI and physical AI chip designers a more production-ready environment. The Virtuoso Layout Suite has added enhanced connectivity models, helping custom design teams start projects more quickly and work with greater accuracy.
On the IP side, Cadence has taped out DDR5, LPDDR5, and PCIe 6.0 IP on TSMC N2P. PCIe 3.0 IP for N2P is expected to tape out in the fourth quarter of 2026. UCIe-64G IP for N2P is currently in lab testing and has also been characterized on TSMC N3P.
Cadence has additionally demonstrated a UALink solution in TSMC N3P. UALink is becoming increasingly relevant as AI systems require faster, lower-latency communication between accelerators. This is part of a wider push to support advanced interconnect standards and high-bandwidth connectivity for large-scale AI computing platforms.
The partnership also extends into 3D-IC and advanced packaging, where chipmakers are moving toward larger and more complex multi-die systems. Cadence solutions now support TSMC SoW-X full design flows involving hundreds of chiplets and millions of bumps. This is critical for wafer-scale and near-wafer-scale AI systems, where traditional single-die design approaches are no longer enough.
Cadence tools are also enabled for 5x reticle-size CoWoS-L-style advanced packages. These large packages can integrate multiple advanced components, including SoIC, eDTC, MIMCap, integrated voltage regulators, HBM logic base die, and substrate technologies. Cadence Integrity 3D-IC is used for system planning and assembly, helping design teams manage these increasingly complex multi-die architectures.
Another key advancement is the certification of a pre-simulation-driven die-to-die auto-routing flow. This flow uses Cadence Allegro Substrate Router and Cadence OmniRoute Advanced Interconnect Router to automatically create signal-integrity-optimized routing strategies across CoWoS architectures. The routing flow also targets UCIe requirements, which are important for chiplet-to-chiplet communication in advanced AI and HPC systems.
Cadence is also enabling TSMC-COUPE, a compact universal photonic engine designed for high-bandwidth photonic-to-silicon connectivity. This technology is supported through integration with Cadence 224G SerDes IP. The SerDes IP aligns with emerging ecosystems such as UALink, ESUN, UltraEthernet, and co-packaged optics, while complementing Cadence’s broader HPC and AI IP portfolio.
That portfolio includes HBM4 and HBM4E, LPDDR6 and LPDDR5X, DDR5-MRDIMM, PCIe 7.0, and UCIe 64G. Together, these technologies are aimed at helping customers build the next wave of AI accelerators, data center processors, networking chips, and chiplet-based compute platforms.
Global Unichip Corp. is one of the companies using Cadence solutions for advanced custom silicon on TSMC’s leading-edge technologies. The company is applying Cadence-driven automation to reduce schedule risk and support complex designs for AI accelerators and hyperscale systems.
Louis Lin, senior vice president at Global Unichip Corp., said that as designs move to advanced TSMC nodes such as N3P and N2P, success depends on tightly optimized execution across increasingly demanding system requirements. He noted that Cadence solutions provide the predictability, performance, and silicon correlation needed to deliver and tape out complex designs on advanced process technologies.
The expanded Cadence and TSMC collaboration highlights where the semiconductor industry is heading. AI and HPC chips are no longer defined only by transistor scaling. They now depend on a complete ecosystem that includes certified design tools, proven IP, advanced packaging, chiplet integration, signal integrity, power integrity, and high-speed interconnects.
With certified flows for A14, A16, and N2P, new silicon-proven IP, and 3DFabric support for systems with hundreds of chiplets, Cadence and TSMC are giving chip designers a more complete path from architecture to tape-out. For companies building next-generation AI processors, infrastructure silicon, and wafer-scale systems, the partnership could help reduce process risk, improve power-performance-area results, and accelerate time to market.
