TSMC’s latest packaging innovation is set to propel chipsets developed with its pioneering 3nm process to new heights. Their Small Outline Integrated Circuit Molding-Horizontal (SoIC-MH) packaging technology is designed to enhance both thermal and electrical performance, resulting in improved performance per watt for SoCs. While Apple has reportedly started mass production of its new M5 chips, it’s likely this cutting-edge packaging will first appear in the M5 Pro.
The differentiation in packaging between the M5 and M5 Pro seems to stem from efficiency gains—or lack thereof—between TSMC’s 3nm N3E and N3P technologies, which only offer modest improvements of 5-10 percent. This minor efficiency increase suggests that Apple might maintain the same CPU and GPU core count for the M5 Pro, opting instead to slightly boost clock speeds.
Such minimal changes could lead to negligible differences between the M5 Pro and its predecessor, the M4 Pro, potentially impacting sales. However, by utilizing TSMC’s SoIC-MH, which leverages vertically stacked chips for added circuit layers and enhanced performance, the M5 Pro may stand out as a formidable contender.
There’s optimism that this packaging method could also benefit the M5 Max and M5 Ultra, although the report remains silent on these specifics. As we look forward to seeing these technological advancements in action, it’s essential to remain cautious as details are still emerging. Stay tuned for updates as more information becomes available.
