Exciting developments are rumored to be in the works for AMD’s next-generation Zen 6-based Ryzen “Medusa” CPUs. According to recent chatter on Chinese forums, these upcoming processors are set to feature a significant change in their memory controller configuration, which could impact DDR5 memory orientation.
The buzz suggests that these Zen 6 CPUs will incorporate two integrated memory controllers (IMCs), although it’s currently unclear whether these are dual controllers within the same chip or two distinct units. This new setup is anticipated to alter the preferred orientation for DDR5 memory modules substantially.
Interestingly, it is reported that one of these memory controllers supports only one DIMM per channel (1DPC). This implies that for configurations using this specific IMC, users will be limited to two DIMMs. In contrast, most current AM5 motherboards from AMD utilize A0 and B0 DIMM slots for boot configurations to ensure smooth startup procedures. However, the new IMC orientation will require shifting to A1 and B1 slots, potentially making Zen 6 incompatible with the older 1DPC setup.
For motherboards with four DIMM slots, commonly labeled A2 and B2 as first slots, this new compatibility requirement might mostly affect 2-DIMM board designs like Mini-ITX and mATX, which are popular among overclocking enthusiasts. Fortunately, AMD appears to be working to enable A0/B0 orientations, but performance might not match that of the A1/B1 configuration.
Sources indicate that MSI’s MPOWER AM5 motherboard is already prepared to support this new configuration. However, the full scope of compatibility and performance variations will become clearer once AMD officially announces the Zen 6 Ryzen “Medusa” processors.
Set to release next year, the Zen 6-based builds will not only bring changes to memory configurations but are also expected to offer advancements in core count, cache, and architectural improvements, potentially setting a new standard in desktop processing power. Enthusiasts and tech aficionados are eagerly waiting to see how these innovations will translate into real-world performance.
