Tachyum has put the spotlight back on its Prodigy platform with an ambitious 2nm refresh, touting up to 1024 CPU cores, 6.0 GHz clocks, and head-turning memory and I/O specs aimed squarely at AI and HPC workloads. On paper, the company’s targets even position Prodigy as a challenger to NVIDIA’s planned Rubin Ultra-era systems. But as with past iterations of Prodigy, the boldest numbers are still projections ahead of tape-out.
The company’s CPU roadmap has evolved several times. Earlier versions moved from 128 to 192 to 256 cores per chiplet on a 5nm process with claimed clocks up to 5.7 GHz and an optimistic shipping window around 2027. The new 2nm plan is a much bigger leap, pushing core counts and bandwidth far beyond today’s mainstream server silicon.
Key specifications the company is pitching:
– Process target: 2nm (not yet fabricated)
– Up to 1024 64-bit cores per socket, with clocks up to 6.0 GHz
– Multi-socket scaling up to 16 sockets for as many as 8,192 cores system-wide (1024-core SKU supports up to 8 sockets)
– Up to 1 GB combined L2+L3 cache with ECC on instruction and data caches
– Out-of-order, 8-wide decode/issue microarchitecture with matrix and vector extensions for AI and HPC
– TDP range from 30 W to as high as 1600 W depending on core count/config
– Memory: 24 DDR5 channels, up to 17,600 MT/s, and as much as 48 TB per socket
– I/O: up to 128 PCIe 7.0 lanes and 64 PCIe controllers
Core configurations are planned from 32 all the way to 1024 cores, with corresponding TDPs scaling from tens of watts up to 1.6 kW for the highest-end SKUs. The cache hierarchy includes 128 KB instruction cache and 64 KB data cache per core (both ECC-enabled), plus a large shared last-level cache to keep those cores fed.
On the platform side, the memory and I/O roadmap is just as aggressive. Support for 24 DDR5 channels at up to 17,600 MT/s and 128 lanes of PCIe 7.0 would put Prodigy far ahead of what’s commonly available in shipping server hardware. Given that DDR5-17600 and PCIe 7.0 are not yet standard in the market, bringing a full platform like this to customers by 2027 seems improbable; delivering it by 2030 would still be a stretch without extraordinary execution.
Tachyum’s performance claims are equally bold. The company says a Prodigy configuration could surpass 1000 PFLOPs on AI inference—compared to about 50 PFLOPs cited for forthcoming Rubin-class systems. It also projects massive rack-level advantages:
– Prodigy Ultimate: up to 21.3x higher AI rack performance versus Rubin Ultra (NVL756)
– Prodigy Premium: up to 25.9x higher AI rack performance versus Rubin (NVL144)
What exactly differentiates Prodigy Premium from Prodigy Ultimate isn’t fully explained; they may be separate SKUs or different rack architectures. Either way, the claims hinge on future products from both sides, and the company has yet to demonstrate silicon.
The reality check: despite an infusion of around $220 million and assurances that tape-out is near, Prodigy remains a pre-fabrication design with no publicly shipped hardware. The specs are tantalizing for data centers chasing AI throughput, high memory capacity, and extreme multi-socket scaling—but they’re still aspirations. If Tachyum can execute, it could offer a CPU-centric alternative for AI inference and HPC that compresses GPU-like performance into general-purpose silicon. Until real chips land in labs, though, these numbers should be treated as targets rather than guarantees.
Bottom line: the 2nm Prodigy vision is dramatic—1024 cores, 6 GHz clocks, terabytes of DDR5 per socket, and PCIe 7.0 bandwidth—but timelines and feasibility remain the biggest questions. The next meaningful milestone will be a successful tape-out and working prototypes that validate the performance claims in the real world.
