TSMC and NYCU Report Breakthrough That Could Shape the Future of 2D Transistors
Taiwan Semiconductor Manufacturing Company, better known as TSMC, has teamed up with National Yang Ming Chiao Tung University in Taiwan to demonstrate an important advance in next-generation transistor technology. The research focuses on one of the biggest challenges facing the semiconductor industry: how to keep improving transistor performance as chip components become almost unimaginably small.
Instead of trying to solve the problem by simply adding new materials on top of the transistor channel, the researchers took a different approach. They engineered the channel surface itself before applying the insulating layer and gate structure. This method creates an ultra-thin buffer that helps the gate control electron flow more effectively while reducing leakage.
The work is especially important because modern chips are reaching the physical limits of existing transistor designs. Today’s advanced processors generally use FinFET or gate-all-around transistor structures. These three-dimensional designs improved performance by wrapping the gate around the channel, giving the gate more control over current flow. In a transistor, the channel carries the current, while the gate acts like a switch that regulates how that current moves.
However, as chipmakers continue shrinking transistor dimensions, controlling electron flow becomes more difficult. When channel lengths approach the 3-nanometer to 5-nanometer range, the gate can struggle to manage the current properly. At the same time, when channel thickness falls below around 3 nanometers, electrons can interact too closely with the gate, increasing resistance and reducing efficiency.
This is why researchers are paying close attention to two-dimensional transistor materials. These materials can be just one molecular layer thick, offering the potential for thinner channels, improved gate control, lower resistance, and higher transistor density. In theory, 2D transistors could allow channel thicknesses around 0.7 nanometers and channel lengths below 3 nanometers, making them attractive for future semiconductor manufacturing.
One promising material is monolayer molybdenum disulfide, or MoS₂. It naturally has a thickness of around 0.7 nanometers and offers strong potential for controlling current in ultra-small transistor designs. But MoS₂ also creates manufacturing challenges. Traditional methods for depositing the gate dielectric layer can produce uneven coverage on the channel surface, which weakens performance and increases leakage.
TSMC and NYCU’s breakthrough addresses this issue by focusing on the interface between the MoS₂ channel and the gate dielectric layer. The gate dielectric is a critical insulating layer that prevents current leakage while allowing the gate to control the transistor. Rather than relying on entirely new deposition methods or replacing materials wholesale, the team used an ultrathin epitaxial aluminum layer to prepare the MoS₂ surface.
The process begins by depositing a very thin layer of aluminum directly onto the MoS₂ channel. This aluminum is then allowed to oxidize, forming a 0.42-nanometer-thick layer of aluminum oxide. After that, the researchers add a high-κ hafnium oxide gate dielectric layer on top.
This engineered buffer layer helps create a cleaner and more effective interface for the gate dielectric. As a result, the transistor shows improved current control and reduced resistance. According to the research, the performance is comparable to what would be expected from a dielectric layer with an effective thickness of about 1 nanometer.
The significance of this development lies in its practicality. Future chips will need transistor designs that can maintain strong electrical control even as dimensions shrink far beyond today’s mainstream manufacturing nodes. If 2D materials like MoS₂ can be integrated more reliably into semiconductor production, they may help extend chip scaling and support more powerful, energy-efficient processors.
For TSMC, the research highlights the importance of materials engineering in the next stage of semiconductor innovation. As the industry moves beyond conventional silicon-based scaling, breakthroughs at the atomic and molecular level will become increasingly important. Better gate control, lower leakage, and reduced resistance are all essential for building faster chips that consume less power.
While this does not mean MoS₂ transistors are ready for immediate mass production, the demonstration marks a meaningful step toward future 2D semiconductor devices. By solving one of the key interface problems in monolayer transistor design, TSMC and NYCU have shown a possible path for building ultra-thin transistors that could one day power advanced processors, AI accelerators, mobile chips, and high-performance computing systems.
The race to make smaller and more efficient chips is no longer only about shrinking dimensions. It is increasingly about controlling materials at the atomic scale. This research shows that carefully engineering the transistor channel before adding the gate stack may be one of the most promising ways forward.
