Qualcomm has taken an important step toward its next-generation AI inference hardware, confirming that its first-generation High Bandwidth Compute silicon has been validated in the company’s San Diego lab. The early silicon test gives Qualcomm its first hardware-backed proof point for a memory architecture designed to tackle one of the biggest bottlenecks in large language model inference: memory bandwidth.
The validation involved the full memory read-and-write path, along with near-memory compute functions, running at dimensions intended to reflect production conditions. Qualcomm says the testing used industry-standard automated equipment with randomized weights and activations, suggesting the company is moving beyond theoretical projections and into practical silicon evaluation.
At the center of Qualcomm’s approach is the idea that AI inference performance is increasingly limited not only by raw compute power, but by how quickly data can reach that compute. Every token generated by a large language model requires model data to move into the processing units. At data center scale, that constant data movement can create major penalties in latency, energy use, throughput, and overall operating cost.
Qualcomm’s High Bandwidth Compute, or HBC, technology is designed to reduce those penalties by bringing memory and compute much closer together. Instead of relying on traditional memory layouts where data must travel longer distances across a package or board, Qualcomm stacks low-power LPDDR memory dies directly on top of an active AI accelerator base die. This is done using wafer-to-wafer bonding, a technique that can reduce the distance data travels from millimeters to micrometers.
That shorter path is central to the claimed performance benefits. Qualcomm says its HBC design delivers an 18-times increase in effective memory bandwidth compared with LPDDR5X. The company also claims more than five times better bandwidth per watt than projected HBM4 specifications, positioning the technology as a potential alternative for future AI inference systems where efficiency matters as much as speed.
However, Qualcomm’s latest efficiency figure appears to fall slightly below its earlier target of six-times improvement. The company notes that these numbers are based on measured silicon results normalized to target operating conditions and compared with published competing product specifications. Final performance may vary depending on implementation, workload, and system configuration.
Qualcomm is presenting HBC as part of a broader, multi-stage development roadmap. The program includes architecture design, process development, test vehicles, silicon validation, and eventual product integration. The company also says it has worked with foundry and assembly partners to qualify wafer-to-wafer bonding for this type of stacked memory design.
Reliability is another major part of the effort. Stacking memory layers on logic can introduce manufacturing challenges, including defects in individual layers. Qualcomm says its HBC design includes redundancy and remapping features, allowing the system to work around faulty memory areas rather than failing outright. That kind of fault tolerance will be important if the technology is to scale into commercial AI infrastructure.
The company also points to its long history in memory-on-logic development. Qualcomm says it has spent more than a decade working on related technologies, including direct bonding of DRAM onto logic and contributions to LPDDR memory standards. That background may help the company as it attempts to bring stacked low-power memory into high-performance AI systems.
Commercial versions of Qualcomm’s HBC products are expected to move from the two-layer memory stack used in early work to a four-layer DRAM stack. This should increase memory capacity and bandwidth, making the design more suitable for large-scale AI inference workloads.
One of the first major products expected to use this technology is the Dragonfly AI250, which Qualcomm is targeting for sampling in the first half of 2027. The AI250 is expected to become part of Qualcomm’s Dragonfly Rack inference infrastructure, a full liquid-cooled rack platform designed for high-density AI deployment.
According to Qualcomm’s current plans, the Dragonfly Rack configuration will include 38.6TB of memory and deliver 7.4 petabytes per second of effective memory bandwidth. Those numbers highlight the company’s ambition to compete in data center AI inference, a market where memory bandwidth, energy efficiency, and system-level scaling are becoming critical differentiators.
Qualcomm’s broader server roadmap is also taking shape. The company plans to introduce its Oryon-based C1000 server CPU in 2027, followed by a next-generation HBC implementation in the Dragonfly AI300 in 2028. Together, these products suggest Qualcomm is preparing a more aggressive push into AI server infrastructure, expanding beyond its traditional strengths in mobile and edge computing.
Still, it is important to treat these results as early-stage data. The validation was performed in Qualcomm’s own lab using early silicon, and real-world performance could differ once final hardware is tested in independent environments and production systems. Workloads, cooling, software optimization, and full rack-level deployment can all affect actual results.
Even so, Qualcomm’s HBC validation is a notable milestone. If the company can translate these early results into reliable commercial products, its stacked memory approach could offer a compelling path for improving AI inference performance while reducing power demands. With the Dragonfly AI250 planned for 2027 and the AI300 expected in 2028, Qualcomm is clearly positioning high-bandwidth, near-memory computing as a key part of its future AI data center strategy.
