Intel May Use Dual-Side Power Delivery for Its 14A2 Chip Process as Scaling Challenges Grow
Intel is reportedly exploring a major change for its upcoming 14A2 semiconductor manufacturing process, as the company works to close the gap with leading foundries in advanced chip production. The shift involves using both front-side and back-side power delivery, a move that could help Intel manage increasing complexity as chip features become smaller and harder to manufacture.
The reported change is tied to Intel’s next-generation 14A process family, particularly the 14A2 version. This node is expected to be a key part of Intel’s effort to compete with advanced process technologies from TSMC and Samsung Foundry, including TSMC’s N2 family and Samsung’s SF2Z platform.
Why power delivery matters in advanced chips
In modern semiconductor manufacturing, power delivery is one of the biggest challenges. Traditionally, power and signal lines are routed through the front side of a chip, where the transistors are located. However, as chips become denser, this approach can create congestion and limit performance.
Back-side power delivery helps solve that problem by moving power routing to the back side of the wafer. This frees up valuable space on the front side for signal wiring and transistor placement. The result can be better transistor density, improved performance, and reduced voltage loss.
Intel has already placed significant focus on back-side power delivery as part of its advanced node strategy. However, the company may now be considering an even more complex approach for 14A2: using both front-side and back-side power delivery at the same time.
The challenge comes from shrinking metal interconnects
The reported reason for this possible shift is the shrinking size of the M0 metal pitch. In chip design, M0 refers to one of the lowest metal interconnect layers, which helps transmit signals between transistors. The smaller the M0 pitch, the more tightly packed the circuitry can become.
For Intel’s 14A process, the M0 pitch is reportedly expected to be around 28 nanometers. With 14A2, that could shrink to approximately 21 nanometers. This reduction would allow Intel to increase transistor density and improve the economics of using expensive High-NA EUV lithography machines.
However, shrinking these structures also makes manufacturing more difficult. Narrower interconnects can increase electrical resistance, which may lead to voltage drops. These voltage drops can affect performance and reliability, especially when power is delivered through through-silicon vias, or TSVs, used in back-side power delivery.
Because of this, Intel is said to be evaluating a dual-side power delivery approach for 14A2. By using both sides of the chip for power routing, the company may be able to reduce resistance-related issues while still achieving the density improvements needed for a competitive advanced process.
Intel is racing against powerful foundry rivals
The timing is critical for Intel. TSMC and Samsung Foundry are both moving aggressively with their next-generation process nodes. TSMC’s N2 technology family is expected to become increasingly mature through 2025 and 2026, while Samsung has continued refining its gate-all-around transistor architecture.
Gate-all-around, or GAA, is a major transistor design shift that gives chipmakers better control over electrical current, improving power efficiency and performance. Samsung has already introduced GAA technology in earlier nodes, giving it experience that may help with future process development.
Intel, meanwhile, is trying to regain leadership in semiconductor manufacturing after years of intense competition. Its 14A family is expected to play a central role in that comeback plan. The company reportedly aims to provide 14A0.9 design kits to customers in October 2026, which means it has limited time to finalize key manufacturing choices.
High-NA EUV is central to Intel’s strategy
Intel has been one of the most aggressive adopters of High-NA EUV lithography, a next-generation chipmaking technology designed to create finer circuit patterns. These machines are extremely expensive, so chipmakers need strong transistor density improvements to justify their use.
By reducing the M0 pitch on 14A2, Intel could make better use of High-NA EUV equipment and improve the cost structure of advanced chip production. But the smaller the circuit features become, the harder it is to avoid patterning errors, resistance issues, and power delivery problems.
That is why dual-side power delivery could become an important solution. It may add complexity to the manufacturing process, but it could also give Intel more flexibility as it pushes toward smaller, denser, and more powerful chips.
What this could mean for future Intel chips
If Intel moves forward with dual-side power delivery for 14A2, it would signal how difficult advanced semiconductor scaling has become. Simply shrinking transistors is no longer enough. Modern chipmaking now requires breakthroughs in lithography, transistor architecture, interconnect design, and power delivery.
For Intel, success with 14A2 could strengthen its position in the foundry market and help attract major customers looking for cutting-edge manufacturing options. For the wider chip industry, it highlights the growing importance of power delivery innovation as companies push beyond 2nm-class technologies.
While the decision has not been officially confirmed, the reported consideration shows that Intel is actively evaluating new ways to overcome the physical limits of chip scaling. As the race for next-generation semiconductors intensifies, power delivery may become just as important as transistor density in determining which foundry leads the market.
