Huawei’s Kirin 9050 Pro Shows How LogicFolding Could Reshape Smartphone Chip Design
Huawei appears to be making meaningful progress with its next-generation chip design strategy, and the Kirin 9050 Pro is becoming one of the clearest examples yet. Newly shared die images suggest that Huawei is using an advanced packaging approach known as LogicFolding to reduce chip footprint while improving compute density.
The Kirin 9050 Pro reportedly uses two identical-sized dies bonded together. One die is focused on compute tasks, while the other is dedicated to cache memory and SRAM. This design allows Huawei to separate key chip functions across different silicon layers while making them work closely together as a single integrated unit.
LogicFolding is especially interesting because it stacks logic circuits vertically instead of relying only on traditional horizontal scaling. In simple terms, Huawei is trying to fit more performance into a smaller physical area by building upward rather than just shrinking everything on a flat surface. This can help shorten signal paths, improve communication between chip sections, and increase overall efficiency.
According to the latest die shots, both dies measure 11.13mm by 10.84mm, giving each one an area of around 120.65 square millimeters. That makes the Kirin 9050 Pro slightly smaller than the Kirin 9030S, which reportedly measures around 122 square millimeters.
This smaller footprint could be a major advantage. Smaller dies are often easier to manufacture with better yields, meaning more usable chips can be produced from each wafer. That is particularly important for Huawei as it continues working with domestic semiconductor manufacturing processes under challenging supply conditions.
The Kirin 9050 Pro is said to use two different process technologies from SMIC. The compute die is reportedly manufactured on the N+3 process, while the SRAM die is believed to use the N+2 process. This mixed-node strategy may allow Huawei to balance performance, efficiency, cost, and manufacturing complexity more effectively.
However, the full chip package may still be difficult to produce at high volume. While individual dies could benefit from improved yields due to their smaller size, bonding two active dies together through LogicFolding adds another layer of complexity. This may explain why Huawei is reportedly reserving the Kirin 9050 Pro for its most premium smartphone models, including Pro Max and RS variants.
The use of LogicFolding suggests Huawei is not simply trying to catch up through conventional chip scaling. Instead, the company appears to be exploring advanced chiplet-style and 3D integration methods to overcome limits in transistor density and manufacturing technology.
Previous claims suggested that the Kirin 9050 Pro, despite being built on a process considered roughly comparable to 7nm-class technology, delivered performance results strong enough to challenge Apple’s A18 Pro. While such claims should still be treated cautiously, the newly revealed compact die design makes the performance rumors more plausible than they may have first appeared.
If Huawei can continue improving LogicFolding yields and manufacturing consistency, the Kirin 9050 Pro could mark an important step forward for China’s semiconductor industry. It also shows how future smartphone processors may depend less on traditional node shrinks and more on clever packaging, vertical stacking, and smarter die integration.
For now, the Kirin 9050 Pro stands out as one of Huawei’s most ambitious mobile chips yet. Its smaller footprint, dual-die structure, and use of vertical stacking highlight a bold approach to smartphone processor design at a time when the global chip industry is searching for new ways to boost performance beyond standard silicon scaling.
