The race to smaller, more efficient chip technology is heating up, with MediaTek making strategic moves in the semiconductor industry. As anticipation builds for the first 2nm chips, MediaTek plans to utilize TSMC’s third-generation 3nm process for its upcoming Dimensity 9500 release later this year. However, the real excitement surrounds their announcement to initiate the tape-out of 2nm silicon by the fourth quarter of 2025, aiming to solidify their position as a leading chipset provider.
Interestingly, MediaTek’s first product using this cutting-edge 2nm technology isn’t expected until late 2026. By starting the tape-out in the fourth quarter, the company gains valuable time to refine the chips and ensure a smooth rollout to potential clients. A sneak peek at the tentative Dimensity 9600 indicates a promise of up to 25% efficiency improvement over its predecessors.
For those unfamiliar, the tape-out process marks the final stage of a chip’s design phase. It’s then handed over to the manufacturer, TSMC in this case, for mass production. This stage involves significant financial investment, and if a chip requires adjustments, it must undergo the tape-out process again—a costly endeavor.
A MediaTek executive revealed that the tape-out for these 2nm chipsets would start in September. This timing advantages MediaTek, as TSMC is set to begin orders for its next-gen lithography starting April 1. This head start allows MediaTek to make any necessary tweaks to match the performance and efficiency benchmarks set by competitors like the Snapdragon 8 Elite Gen 2.
The anticipated 2nm System on Chip (SoC) is projected to offer up to 15% better performance and reduce power consumption by up to 25% compared to the N3 node. However, MediaTek hasn’t specified whether this comparison is against the N3E or the N3P variants. Meanwhile, Qualcomm has announced its Snapdragon Summit 2025, scheduled for September 23. Here, we expect the Snapdragon 8 Elite Gen 2 to face off with MediaTek’s advancements, promising an exciting showdown in the semiconductor space.
